In 3D flash memory arrays, memory cells and wordlines are stacked vertically in tiers of memory cells. To access and control the wordlines, sides of memory arrays are terminated with one or more staircase structures, to allow connection metal contact structures to be connected to the wordlines. The staircase structures include a step or landing for each wordline, to connect each wordline to a metal contact. To increase the density of memory arrays, memory manufacturers are attempting to add additional tiers of memory cells into the memory arrays. An undesirable side effect of more tiers is an increase in size of the staircase that is used to electrically connect to, access, control the wordlines of the memory array. The staircase, while important in function, consumes silicon real estate and interferes with the goal of shrinking die sizes or increasing die densities.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.